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"Ask the Experts" is moderated by Béla Lipták, process control consultant and editor of the Instrument Engineer's Handbook (IEH). The 4th edition of Volume 3, Process Software and Networks, is in progress. If you are qualified to contribute to this volume, or if you are qualified to answer questions in this column or want to ask a question, write to email@example.com.
Q: I am running an experiment with a level control loop, and I found a problem with the performance of the controller when I change the control mode, because it considers that as a disturbance.
For example, I start the experiment using a PI controller, and the level goes to steady state and equal to the setpoint. Then I want to change to proportional-only control, so I delete the integral term, but at this instant the level starts changing, reaching another steady state. I always thought that disturbances come from changes in the setpoint or loads, but not from control mode changes. Could you please explain this to me?
I tried two things:
In both cases, when the integral is deleted, the controller output suddenly goes to zero. Then it goes to other values, causing the process variable to change.
There are two basic types of digital algorithms, positional and velocity. With positional the full output is recalculated every cycle: m = Kc (e + ∑edt/Ti + Td ∆e/∆t) + b.
When velocity algorithm is used, the value of the previous output signal (m) is held in memory, and every cycle only the required change in that output signal is calculated: ∆m = Kc (∆e + e∆t/ Ti + Td ∆(∆e/∆t).
It seems that you have a badly designed positional algorithm. A PID algorithm shouldn't change its output because of a change in the control modes. This is a bad algorithm. The programmer who put it into the PLC should be fired.
Actually, it would be even more useful if the association of the instrument manufacturers provided some kind of certification for all control and measurement instruments, so that the users could check if the supplier's claims (including accuracy, rangeability, etc.) were correct.
A: When you reach a steady state at setpoint by means of integral action, the controller output and its internal bias will match the current process load. The controller you are using apparently switches to proportional, using a fixed bias, when you delete the integral mode. If that fixed bias is different from the existing output, it will bump the output to that bias value, thereby upsetting the loop. Setting the proportional controller's bias equal to the output before deleting the integral mode would eliminate this effect.
The disturbance you see is not the result of tuning, but of switching controller modes. If you were to increase integral time to its maximum value instead of deleting it, no bump should result. (However, some PID controller designs do cause a change in output when the proportional gain is changed, and that is undesirable.)
Your controller is either defective or designed incorrectly—get another one. The behavior you describe will not happen with a well-designed controller. The transition will be bumpless.
A: This is most likely a problem with the PID aglorithm. A well-designed PID controller would not immediately bump the output on changing the integral term. Changing proportional gain would change the output right away.
A: It appears as though the calculation of the PID formula is a very primitive structure like this:
e = (Ysp-Y)
I = I + e*dt
m= Kc*e + Kc*I/Π)
in which the integral term is the bias. Certainly, when the process is at setpoint, and e = 0, if the integral term is removed, then the bias is removed, and the output calculation is based on m = Kc*e, which is zero.
There are many ways that software developers can solve this problem, and it is a curious situation to think that a PLC manufacturer would not have provided a better algorithm. Perhaps Ghanima could choose another PI variant from the ones offered on the PLC.
R. Russell Rhinehart, PhD
A: Given the constraints that seem to be in place, the only possibility I can see is to solve this problem is for the questioner to set up multiple controllers with their PV and SP inputs paralleled and select the output he wants at the time he wants.
Obviously, the outputs would only be relatively matching (for bumpless transfer) when process conditions, controller mode and tuning dictated.
In fact, how often they matched, or their convergence, might give him some input on the feasibility of what he is trying to do.
I use the term "bumpless" because of the modern controller feature called "bumpless transfer," which reduces such output changes after a controller auto-manual or mode switch.